100 MHz maximum clock rate
20 channels with per-cycle, per-channel bidirectional control
-2.0 to 5.5 V voltage levels, programmable in 10 mV steps
Real-time hardware comparison of acquired response data
1, 8, or 64 Mb/channel onboard memory
NI Synchronization and Memory Core (SMC) device for subnanosecond multidevice synchronization